1. Field of the Invention
The present invention relates to a layout design method of a semiconductor integrated circuit.
2. Description of Related Art
In recent years, an automation of analog layout design has progressed and a design period has been shortened. As a method of automating analog layout design, known is cross-probing that enables layout design while associating elements on a circuit diagram editor respectively with elements on a layout editor. Here, in order to perform layout design by cross-probing, it is necessary to create mapping information associating an element on the circuit diagram editor with a cell including an element on the layout editor.
For example, when making design revision using already-existing layout data, the design is generally performed by reading a layout into a design system via a mask pattern file in a binary form typically used for storing layout information (hereinafter, referred to as GDS2). Moreover, when using a layout designed by a different design system or using a layout data which is not designed in a circuit diagram-driven manner, it is necessary to create mapping information and then to read the mapping information into an integrated design system functioning as a circuit diagram editor and a layout editor. However, creating mapping information is difficult, and therefore a technology which facilitates mapping is required.
FIG. 5 is a system chart showing an embodiment of a layout verification method and a circuit simulation method described in FIG. 1 of Patent Document 1. As shown in FIG. 5, in the layout verification method and the circuit simulation method, prepared is, as an external tool, a SPICE netlist extraction tool 1 which can accurately extract a parasitic capacity, a resistance value and the like of a layout. The SPICE netlist extraction tool 1 processes a layout pattern 3 corresponding to circuit diagram data 2 to create a SPICE netlist 4.
With the process of creating the SPICE netlist 4, a netlister 5 reads the circuit diagram data 2 to be processed, performs an extraction process of a netlist, and thereby creates a circuit diagram netlist 6. Thereafter, a net comparer 7 performs a process of comparing the contents of the SPICE netlist 4 and the contents of the circuit diagram netlist 6. A SPICE vs circuit diagram node association table 8 and a verification result 9 are then created.
Moreover, in parallel with this process, a circuit simulator 10 performs a circuit simulation process based on the SPICE netlist 4 to create a circuit simulation result 11. When these processes are complete, a display portion 12 for displaying simulation result by cross-probing on the circuit diagram and LVS result displays the contents of the cross-probing of the circuit simulation result on a screen, based on the circuit simulation result 11, the SPICE vs circuit diagram node association table 8, and the circuit diagram data 2. At the same time, a result of LVS is displayed on a screen with a circuit diagram, based on the circuit simulation result 11, the verification result 9, and the circuit diagram data 2.
In Patent Document 1, a net comparison is made by comparing the SPICE netlist 4 extracted from the layout pattern 3 by the SPICE netlist extraction tool 1 is compared, with the circuit diagram netlist 6 extracted from the circuit diagram data 2 by the netlister 5. The SPICE vs circuit diagram node association table is then created to perform cross-probing.    [Patent Document 1] Japanese Patent Application Publication No. Hei 9-044559